1. Field of the Invention
This invention relates to a semiconductor memory circuit, and particularly to a data write circuit suitable for use in a ROM such as an EPROM (Erasable Programmable Read Only Memory) or an OTPROM (One Time Programmable Read Only Memory).
2. Description of the Background Art
With the objective of achieving mass storage capacity of a semiconductor memory device, there has recently been a tendency to increase the number of memory cells contained in one subarray of the semiconductor memory device and increase even the number of subarrays. With their increases, cell source lines are extended in length, thus leading to an increase in the capacitive component of each cell source line. The capacitive component developed in the cell source line has brought about a possibility that upon selecting a predetermined memory cell and writing H level data therein, L level data not to be originally written would be written into each non-selected memory cell connected to a word line corresponding to the selected memory cell. In this case, cell source line selection transistors corresponding to the non-selected memory cells are turned off so that their corresponding cell source lines are respectively held in a floating state. However, when the capacitive components of these cell source lines are large, a transient current will flow in the non-selected memory cell transistors. Avalanche breakdown occurs due to the transient current so that hot electrons are injected into the floating gates of the non-selected memory cell transistors, thereby increasing threshold voltages of these transistors. Further, these transistors increase in operation minimum source voltage, so that there was a possibility that the L level data not to be written would be written into the non-selected memory cells.